Sampled data simulator control system



Nov. 10, 1964 J. E. REICH ETAL 3,156,899

SAMPLED DATA SIMULATOR CONTROL syswsm Filed May 24, 1962 4 Sheets-Sheet1 T SAMPLING PULSEE:

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OUTPUT FROM CHANNEL} 5AMPLE \NPUT TO CHANNEL]. HOLD INVENTORS OUTPUTFROM CHANNEL}. HOLD QE/CH PM) {\NPUT TO CHANNELll-SAMPLE JAM/55 PEREZ BYOUTPUT FROM CHANNELIL-SAMPLE. 2 [9 \NPLJT TO QHANNELIL HOLD P [P cx)]OUTPUT FROM CHANNELII HOLD AGENT United States Patent 3,156,899 SAMPLEDDATA SIMULATOR CONTROL YSTEM Jerald E. Reich, Lynwood, and James J.Perez, Torrance, Califi, assignors to Space Technology Laboratories,Inc., Redondo Beach, Calif., a corporation of Delaware Filed May 24,1962. Scr. No. 197,502 6 Claims. (Cl. 340-172.5)

This invention relates generally to sample data systems and, moreparticularly, to a sampled data simulator for simulating control systemproblems containing both continuous and sampled information by usingsample and hold techniques.

A sampled data system is defined as a system in which data appears at apoint or plurality of points and then presented in a discontinuousmanner. The process which converts the continuous input data into adata-hold sequence is called the sample process. This invention isconcerned with the control and function of a plurality of discreetsampled data channels and the interconnection of these channels toperform tasks presently being performed on general purpose digitalcomputers. For example, in the design and manufacture of complex controlsystems it is the practice to use general purpose digital computers incombination with continuous input elements to simulate the operation ofa complete system. A sampled data simulation, using analog-to-digitalconverters, is used to feed a digital computer, which is connected to adigital-to-analog converter. The prior art use of general purposedigital computers as a storage device with delayed output is extremelywasteful of resources and, of course, expensive.

In this invention individual sample-hold channels are used directly incombination with the simulating analog input device. The controlling,synchronization and operation of the sample-hold channels in combinationwith the analog input devices is the subject matter of the presentinvention.

Further objects and advantages will be made more apparent by referringnow to the accompanying drawings wherein:

FIG. 1 is a graph illustrating a continuous data input signal withsampling and hold pulses;

FIG. 2 is a schematic diagram illustrating a sample and hold channel;

FIG. 3 is a block diagram of a pair of channels interconnected toperform a basic computer connection known as a transport delay;

FIG. 4 is a graph illustrating the delay obtained by the system of FIG.3; and

FIG. 5 is a block diagram illustrating a sampled data control system.

Referring now to FIG. 1, there is shown a sampled data curve and therelation it bears to a continuous analog input signal 11. The sampleddata curve 10 illustrates the basic requirement of a sampled datachannel having a zero order hold, which is to sample a continuous inputsignal periodically in order to produce an output signal that changes inmagnitude in a staircase-step manner at the sampling times. The sampleddata curve 10 is obtained by controlling a sample data channel.illustrated in FIG. 2, with a train of sample pulses 12 having a periodof time T, followed by a train of delay hold pulses 13, sometimes calledpresent pulses. The hold pulses 13 are of the same frequency as thesampling pulses 12 but delayed therefrom by a fixed time T. The delaytime T is made longer than the width of an individual sampling pulse butless than the period time between successive sampling pulses. This is toinsure the completion of the sampling step before sending a hold pulseand also that a complete sample and hold operation is completed beforethe next subsequent sampling pulse is transmitted. The operation andcontrol of the sampled data channel by the sampling pulses 12 and thehold pulses 13 will be explained in connection with FIG. 2.

Referring now to FIG. 2, there is shown a representative sampled datachannel 14, comprising a sampling circuit 15 and a holding circuit 16.The sampling circuit 15 and the hold circuit 16 are zero holdingcircuits con nected in cascade. The sampling circuit 15 is connected tothe continuously varying analog input signal 11 and is arranged tosample the input signal; whereas, the hold circuit 16 is connected tothe output of the sampling circuit and is arranged to hold and store thesampled information for presentation. The sampled data channel beingdescribed utilizes high speed relays operating at the sampling rate,which in the preferred embodiment are limited to a maximum samplingfrequency of 10 cycles per second. The design of the sampling circuit 15and the hold circuit 16 is within the state of the art and providessatisfactory operation in the desired frequency range of .05 to 10cycles per second. The sampling circuit 15 consists of a resistor 17connected at one end to the continuously varying analog input signal 11and at the other end to a junction of a relay-operated switch 18 and asecond resistor 19 that may be the same as resistor 17. A high gainamplifier 21 is connected across the capacitor 20, forming a junction atone end that is connected to the other side of switch 18. The junctionof resistor 19, capacitor 20, and amplifier 21 forms the output of thesampling circuit, as represented by terminals 22. The amplifier 21 isarranged to hold the charge on capacitor 20 while the switch 18 isopened.

' The switch 18 is operated by a sampling relay 23 in response to thesampling pulses 12. When switch 18 closes, the circuit becomes a firstorder lag and the output terminals 22 charge to the amplitude of theanalog input signal 11 in an exponential manner. The lag time constantis equal to the value of RC, with R value being that of resistor 19 andthe C value being that of capacitor 20. The ratio of the feedbackresistor 19 to the input resistor 17 determines the gain of the sampleamplifier circuit. When switch 18 is opened, the amplifier 21 iseffectively an integrator with no input signal, thereby keeping theoutput signal at terminals 22 equal to the charge on the capacitor 2!).The amplifier 21 will hold the charge on the capacitor 20 until thesampling relay 23 is again operated, allowing the capacitor to charge toa new voltage level. The RC value can be minimized until it is equal tothe rise time of the amplifier 21. The closure time of contacts 18 wasselected to be a factor of ten greater than the RC time constantselected. The hold circuit 16 is constructed of identical elements justdescribed for the sampling circuit 15 and, hence, similar numbers foridentical parts are used. The output of the hold circuit 16 is availableat terminals 24. The bold relay 25 is similar to the sampling relay 23and is controlled by the hold pulses 13. In many operations the analoginput signal does not start at zero due simply to the problem beingsampled. Before a simulation is begun it is necessary, therefore, toread the initial condition signal into the hold amplifier 16. This isaccomplished by means of a relay 26 that controls a single pole doublethrow switch 27. The impulsing of relay 26 not only transfers switch 27to an initial condition input terminal 28 but also controls a singleshot multivibrator circuit 29 which impulses the hold relay 25. Theimpulsing of the hold relay 25 closes switch 18, thereby allowing thehold circuit 16 to sample and hold the initial condition signal beingfed from input 28. As will be described later, a preset program controlwill impulse relay 26 and release the relay control signal prior to thestarting of the computer.

In operation of the complete sampled data channel, the output from thesampling circuit is stored in the hold circuit 16 to prevent loss of thesampled data until the next sample pulse 12 operates the sample relay23. Transfer of the information from the sample circuit 15 to the holdcircuit 16 is achieved by means of the delay 1 existing between the holdpulse 13 and the sampling pulse 12. In the preferred embodiment the holdsignal is achieved by simply delaying the sampling signal the desiredamount.

The timed relationship between the sampling pulses fed to relay 23 andthe holding pulses fed to relay 25 insures that switch 18 of the holdcircuit 16 will be opened while the sampling circuit is sampling theinput signal 11 and that switch 18 of the sampling circuit 15 will beopened while the hold circuit 16 is receiving the signal sampled by thesampling circuit 15. The delay 7' between the sampling signal 12 and theholding signal 13 may be varied a factor of ten greater than the RC timeto a maximum determined by the period of sampling pulses. Individualchannels may be cascaded to obtain a sample period delay per channel Tplus a small hold relay 'r. The advantages of using separate sample datachannels are more pronounced in solving high order difference equationsand in situations involving several sampled data simulations being runconcurrently. For example, a method of solving difference equations mayconsist of cascading N +1 sampled hold channels to thereby obtain Nsampling period transport delay. Since all of these sampling operationsmust be completed in a small fraction of the total sampling period, themaximum sampling rate is dependent on the order of the differenceequation being mechanized.

Referring now to FIG. 3, there is shown a transport delay of N samplingperiods obtained by cascading N +1 sampled data channels. Wave formsillustrating the transmission of an arbitrary wave through channel oneand channel two are more fully illustrated in FIG. 4. It will also beapparent that sampling by channel two of the hold signal in channel oneresults in a one period transport delay. Each of the channels one andtwo contains identical sampling circuits and holding circuits 31. Duringthe n sampling period of T seconds duration, each sample circuit outputconsists of a varying component occurring when the sampling switch 32 isclosed and a constant value when the switch is opened. Thus, for thesampling amplifier:

The differential equations describing the components of the amplifieroutput are:

Considering the case in which T RC and h, with 11/ RC =constant theLaplace transform of the sample amplifier output then becomes Y..(s))X(s) The input quantity x(!) may be a continuous time function or maybe the output of a sample or hold amplifier zero order hold. The sampleamplifier output appears at s, while p is the hold amplifier output.

The following notation is introduced to describe the operationcharacteristics of the sample hold channel, as illustrated in FIG. 4.

(5) S[x(nT)]=-S(x) =sampled and held value of a channel input. x at then sampling instant (6) P xt'nfn flm sampled, held, and delayed (by 1-seconds) value of the channel input, x at the ti sampling instant.

The explanation will be more readily apparent when it is recognized thatthe z-transform of the sampled time function is the Laplace transform ofthat function with the Laplace operator replaced by the identity:

The sampling and hold operators defined by Equations 5 and 6 have thefollowing z-transform properties when the sampled hold channel is notfollowed by a continuous transfer function as follows:

(a) the sampled circuit output with X(z) input (b) the hold output withX(z) input and hold delay of 1- seconds (c) the sampling circuit outputwith P LX(z)] input l i )ll= Referring now to FIG. 5, there is shown ablock di agram of a control system for operating two groups of sampleand hold channels at different frequencies and in synchronism with aremote analog computer. In the preferred embodiment a timing device 35generates a train of clock pulses at the highest repetition samplingfrequency desired. The input for the lower frequency channel is obtainedby dividing the higher frequency by some integral number, thereby makingboth channels coherent with each other. The output of the timing device35 feeds a start control circuit 36 which controls the starting of aremote analog computer 37 in synchronism with the generation of thesampling pulses from the output of the individual channels. This isnecessary to start the running of the simulation with the generation ofthe first sample pulse so as to prevent a fraction sampling intervalduring the first sample period. Before the computer 37 is started allsampling relays and holding relays are energized to clear any initial orresidual voltage being held in the sample or hold amplifiers. Clearingcan be accom plished manually by having the operator control a manualcontrol switch 38 which operates a clearing network 39. The output ofthe clearing network 39 feeds a plurality of power amplifier circuits4!], 41, 42, and 43 being used to impulse all sample and hold relays inthe various channels. The result is that a sample of zero inputinformation is obtained, thereby clearing the sample and hold channelsbefore beginning the simulation.

For those problems requiring the read-in of a fixed constant value forestablishing initial conditions, an initial condition relay 34 isenergized to read the initial condition value directly into theassociated hold amplifier. The clearing network 39 may consist of acontrol relay having contacts for applying an operating voltage to thepower amplifier circuits 4! 41, 42, and 43. In the normal opera tion,the start control 36 is programmed to initially operate the clearingnetwork 39 and read in initial conditions before the computer 37 isenergized, thereby making the operation more automatic for the moreroutine sampling problems. For those problems requiring a randomsampling rate it is possible for the operator to manually andarbitrarily control the manual control switch 38 and thereby supply therandom sampling rate. After the start control 36 has impulsed theclearing network 39, the output of timing device 35 simultaneouslystarts the analog computer 37 and feeds the high frequency channels ofoperation 44 and a frequency divider 45. The frequency divider 45reduces the frequency to a desired repetition frequency which is fed toa junction 46 feeding the low frequency channels.

The driving circuits for the high frequency channels and the lowfrequency channels are substantially the same and must satisfy the sameinput and output requirements. For example, the clock pulses from thetiming device 35 are reshaped in a pulse shaper before being fed to anyof the power amplifiers in order to insure that the sampling and holdrelays will stay closed for a period of 10 RC. In the high frequencychannels the clock pulse is fed to a hold delay 48 and a pulse shaper47, which feeds the power amplifier 40 to emit the sample pulse output.The hold delay 48 is longer than the pulse width of the sampling pulseto insure the sample amplifier is not sampling when a hold pulse is sentto the hold amplifier. The output of the hold delay 48 feeds a pulseshaper 49 which feeds the power amplifier 41 to emit the hold pulseoutput. In the low frequency channels the clock ulse feeds a pulseshaper 50 which feeds the power amplifier 42 to emit the sample pulses.The hold pulses are generated by the clock pulse feeding a hold delay 51as mentioned above, which feeds a pulse shaper 52 and, in turn, thepower amplifier 43.

This completes the embodiment of the invention illustrated herein;however, many modifications and advantages thereof will be apparent topersons skilled in the art without departing from the spirit and scopeof this invention. Accordingly, it is desired that this invention not belimited to the particular details of the embodiment disclosed herein,except as defined by the appended claims.

The embodiments of the invention in which an exclusive property orprivilege is claimed are defined as follows:

1. A sampled data simulator comprising:

a plurality of sample and hold circuits each adapted to be controlled bya sample pulse and a hold pulse respectively,

timing means for generating a train of clock pulses at a givenrepetition rate,

means responsive to said clock pulses for generating a train of samplepulses coherent with said clock pulses, said sample pulses having apulse width suificient to allow sampling of an input signal by saidsampling circuits,

means for controlling said sample circuits with said sample pulses,

means responsive to said clock pulses for generating a train of holdpulses coherent with said clock pulses, said hold pulses being delayed apredetermined time greater than said pulse width of said sample pulseand less than the period time of sample pulses,

means for controlling said hold circuits with said hold pulses, and

means for synchronizing the starting of an external signal simulatingdevice with said timing means, whereby said sample and hold pulses arecoherent with the starting of said simulating device.

2. A sampled data simulator comprising:

a plurality of sample and hold circuits, each adapted to be controlledby a sample pulse and a hold pulse respectively,

timing means for generating a train of clock pulses at a givenrepetition rate,

means responsive to said clocl: pulses for generating a train of samplepulses coherent with said clock pulses, said sample pulses having apulse width sufiicient to allow sampling of an input signal by saidsampling circuits,

means responsive to said clock pulses for generating a delayed train ofhold pulses having the same frequency and the same pulse width as saidsample pulses, said hold pulses being delayed a predetermined timesufiicient for said sampling circuit to have sampled said inputinformation, and

means for synchronizing the start of an external signal simulatingdevice with said timing means whereby the first of said sample pulses iscoherent with the starting of said simulating device.

3. A sampled data simulator comprising:

a plurality of sample and hold circuits, each adapted to be controlledby a sample pulse and a hold pulse respectively,

timing means for generating a train of clock pulses at a givenrepetition rate,

means responsive to said clock pulses for generating a train of samplepulses coherent with said clock pulses and at the same repetition rateof said clock pulses, said sample pulses having a pulse width sufiioientto allow sampling of an input signal by said sampling circuits,

means responsive to said clock pulses for generating a delayed train ofhold pulses saving the same frequency and the same pulse width as saidsample pulses, said hold pulses being delayed a predetermined timesuificient for said sampling circuit to have sampled said inputinformation, and

means for synchronizing the starting of an external signal simulatingdevice with said timing means whereby the first of said sample pulses iscoherent with the starting of said simulating device.

4. A sampled data simulator comprising:

a plurality of sample and hold circuits, each adapted to be controlledby a sample pulse and a hold pulse respectively,

timing means for generating a train of clock pulses at a givenrepetition rate,

means responsive to said clock pulses for generating a train of samplepulses coherent with said clock pulses, said sample pulses having apulse width sufficient to allow sampling of an input signal by saidsampling circuits,

means responsive to said clock pulses for generating a delayed train ofhold pulses having the same frequency and the same pulse width as saidsample pulses, said hold pulses being delayed a predetermined timesufficient for said sampling circuit to have sampled said inputinformation,

clearing means connecting all of said sample and hold circuits forsimultaneously controlling all of said sample and hold circuits wherebythe read-in of initial condition information is controlled, and,

means for initially energizing said clearing means and synchronizing thestarting of an external signal simulating device with said timing meanswhereby the first of said sample pulses is coherent with the starting ofsaid simulating device.

5. A sampled data simulator comprising:

a plurality of channels, each channel comprising a sample and holdcircuit adapted to be controlled by a sample and hold pulserespectively,

timing means for generating a train of clock pulses at a givenrepetition rate,

means responsive to said clock pulses for generating a train of samplepulses coherent with said clock pulses, said sample pulses having apulse width suflicient to allow sampling of an input signal by saidsampling circuits,

means for controlling all of said sample circuits in said channels withsaid sample pulses,

means responsive to said clock pulses for generating a delayed train ofhold pulses having the same freuency and the same pulse width as saidsample pulses, said hold pulses being delayed a predetermined timesufiicient for said sampling circuit to have sampled said inputinformation,

means for controlling all of said hold circuits in all of said channelswith said hold pulses, and

means for synchronizing the starting of an external signal simulatingdevice with said timing means whereby the first of said sample pulses iscoherent with the starting of said simulating device.

6. A sample data simulator comprising:

at least a first and second channel, each of said channels comprising asample and hold circuit adapted to be controlled by a sample and holdpulse respectively,

timing means for generating a train of clock pulses at a givenrepetition rate,

means responsive to said clock pulses for generating a first train ofsample pulses coherent with said clock pulses, said sample pulses havinga pulse Width sutficient to allow sampling of an input signal by saidsampling circuits,

means for controlling all of said sampling circuits in said firstchannel with said first train of said sampling pulses,

means responsive to said clock pulses for generating a first train ofdelayed hold pulses having the same frequency and the same pulse Widthas said first train of sampled pulses, said first train of hold pulsesbeing deiayed a predetermined time suflicient for said sampling circuitsto have sampled said input information,

means responsive to said clock pulses for generating a second train ofsample pulses coherent with said ciock pulses and at a frequency that isdifferent from said clock pulses, said second train of sample pulseshaving a pulse width sufiicient to allow sampling of an input signal bysaid sampling circuits,

means for controlling all of said sample circuits in said second channelwith said second train of said sample pulses,

means responsive to said clock pulses for generating a second train ofdelayed hold pulses having the same frequency and the same pulse Widthas said second train of sampled pulses, said second train of bold pulsesbeing delayed a predetermined time sufi'icient for said samplingcircuits to have sampled said input information,

means for controlling said hold circuits in said second channel withsaid second train of bold pulses, and

means for synchronizing the starting of an external signal simulatingdevice with said timing means, Whereby the first pulse of said firsttrain of sample pulses and the first pulse of said second train ofsample pulses are coherent with each other and the starting of saidsimulating device.

No references cited.

1. A SAMPLED DATA SIMULATOR COMPRISING: A PLURALITY OF SAMPLE AND HOLD CIRCUITS EACH ADAPTED TO BE CONTROLLED BY A SAMPLE PULSE AND A HOLD PULSE RESPECTIVELY, TIMING MEANS FOR GENERATING A TRAIN OF CLOCK PULSES AT A GIVEN REPETITION RATE, MEANS RESPONSIVE TO SAID CLOCK PULSES FOR GENERATING A TRAIN OF SAMPLE PULSES COHERENT WITH SAID CLOCK PULSES, SAID SAMPLE PULSES HAVING A PULSE WIDTH SUFFICIENT TO ALLOW SAMPLING OF AN INPUT SIGNAL BY SAID SAMPLING CIRCUITS, MEANS FOR CONTROLLING SAID SAMPLE CIRCUITS WITH SAID SAMPLE PULSES, MEANS RESPONSIVE TO SAID CLOCK PULSES FOR GENERATING A TRAIN OF HOLD PULSES COHERENT WITH SAID CLOCK PULSES, SAID HOLD PULSES BEING DELAYED A PREDETERMINED TIME 